module fsm(
	input 		   rst, clk,
	input 		   din,
	output reg [2:0] out);

reg 	  [2:0]   currentState, nextState;
// parameter
localparam [2:0]   A = 3'b000,
				  B = 3'b001,
				  C = 3'b010,
				  D = 3'b011,
				  E = 3'b100,
				  F = 3'b101;
  
always@(*)
  case(currentState)
	  A: begin
		nextState = (din==0) ? A : B;
		out = (din==0) ? 3'b000 : 3'b100;
	  end
	  B: begin
		nextState = (din==0) ? A : C;
		out = (din==0) ? 3'b000 : 3'b100;
	  end
	  C: begin
		nextState = (din==0) ? A : D;
		out = (din==0) ? 3'b000 : 3'b101;
	  end
	  D: begin
		nextState = (din==0) ? D : E;
		out = (din==0) ? 3'b010 : 3'b110;
	  end
	  E: begin
		nextState = (din==0) ? D : F;
		out = (din==0) ? 3'b010 : 3'b110;
	  end
	  F: begin
		nextState = D;
		out = 3'b101;
	  end
	  default: begin					//undefine states
		nextState = A;
		out = 3'bxxx;
		end
  endcase

always@(posedge clk or posedge rst)
begin
  if(rst)
	currentState <= A;			//the reset state
  else
	currentState <= nextState;
end

endmodule // fsm
